silk.simd.u8x32.
Operations on simd<u8, 32>: thirty-two unsigned 8-bit integer lanes in one 256-bit vector.
When to use#
Use this module to work on thirty-two u8 values at once. Use load and store
to move lanes between a slice and a vector, a lane comparison such as lanesEqual to make
a mask<32>, and silk.simd.mask32 to test that mask.
Details#
The operators +, -, *, /, %, &, |, ^ and ~ apply lane by lane and trap
exactly where the u8 operator traps. Use wrappingAdd or saturatingAdd when
overflow is expected. == is true only when every lane is equal.
Lane 0 is at the lowest address in memory.
Examples#
Find the first matching lane#
import silk.simd.mask32
import silk.simd.u8x32
pub fn main() -> i32 {
let mut values: [u8; 32] = u8x32.toArray(u8x32.splat(0))
values[31] = 3
let hits = u8x32.lanesEqual(u8x32.fromArray(values), u8x32.splat(3))
if !mask32.any(hits) || mask32.firstSet(hits) != 31 {
return 1
}
return 0
}Import as u8x32 with import silk.simd.u8x32 as u8x32.
Public declarations: 46.
LANES#
pub const LANES: usizeThe number of lanes in a vector.
splat#
pub fn splat(lane: u8) -> simd<u8, 32>Returns a vector with every lane set to lane.
fromArray#
pub fn fromArray(lanes: [u8; 32]) -> simd<u8, 32>Returns a vector whose lane i is lanes[i].
toArray#
pub fn toArray(vector: simd<u8, 32>) -> [u8; 32]Returns the lanes of vector as an array, in lane order.
extract#
pub fn extract(vector: simd<u8, 32>, index: usize) -> u8Returns lane index of vector. Traps when index is LANES or more.
insert#
pub fn insert(vector: simd<u8, 32>, index: usize, lane: u8) -> simd<u8, 32>Returns vector with lane index replaced by lane. Traps when index is LANES or more.
load#
pub fn load(lanes: &[u8], offset: usize) -> simd<u8, 32>Reads LANES lanes of lanes starting at offset.
Gotchas#
Traps unless offset + LANES is at most lanes.length. The slice needs no alignment beyond
u8.
store#
pub fn store(lanes: &mut [u8], offset: usize, vector: simd<u8, 32>) -> ()Writes the lanes of vector into lanes starting at offset.
Gotchas#
Traps unless offset + LANES is at most lanes.length.
loadUnchecked#
pub unsafe fn loadUnchecked(pointer: [*]const u8) -> simd<u8, 32>Reads LANES lanes starting at pointer, with no bounds check.
Gotchas#
The caller proves that pointer addresses LANES live lanes aligned to u8.
storeUnchecked#
pub unsafe fn storeUnchecked(pointer: [*]mut u8, vector: simd<u8, 32>) -> ()Writes the lanes of vector starting at pointer, with no bounds check.
Gotchas#
The caller proves that pointer addresses LANES writable lanes aligned to u8.
lanesEqual#
pub fn lanesEqual(left: simd<u8, 32>, right: simd<u8, 32>) -> mask<32>Returns a mask with lane i set where lane i of left is equal to lane i of right.
lanesNotEqual#
pub fn lanesNotEqual(left: simd<u8, 32>, right: simd<u8, 32>) -> mask<32>Returns a mask with lane i set where lane i of left is not equal to lane i of right.
lanesLess#
pub fn lanesLess(left: simd<u8, 32>, right: simd<u8, 32>) -> mask<32>Returns a mask with lane i set where lane i of left is less than lane i of right.
lanesLessOrEqual#
pub fn lanesLessOrEqual(left: simd<u8, 32>, right: simd<u8, 32>) -> mask<32>Returns a mask with lane i set where lane i of left is less than or equal to lane i of right.
lanesGreater#
pub fn lanesGreater(left: simd<u8, 32>, right: simd<u8, 32>) -> mask<32>Returns a mask with lane i set where lane i of left is greater than lane i of right.
lanesGreaterOrEqual#
pub fn lanesGreaterOrEqual(left: simd<u8, 32>, right: simd<u8, 32>) -> mask<32>Returns a mask with lane i set where lane i of left is greater than or equal to lane i of right.
select#
pub fn select(mask: mask<32>, chosen: simd<u8, 32>, other: simd<u8, 32>) -> simd<u8, 32>Returns lane i of chosen where lane i of mask is set, and lane i of other elsewhere.
minimum#
pub fn minimum(left: simd<u8, 32>, right: simd<u8, 32>) -> simd<u8, 32>Returns the smaller lane of each pair.
maximum#
pub fn maximum(left: simd<u8, 32>, right: simd<u8, 32>) -> simd<u8, 32>Returns the larger lane of each pair.
shuffle#
pub fn shuffle(left: simd<u8, 32>, right: simd<u8, 32>, static indices: [usize; 32]) -> simd<u8, 32>Returns a vector whose lane i is lane indices[i] of left followed by right.
Details#
An index below LANES selects from left, and an index from LANES to 2 * LANES - 1
selects from right. The indices are static, so each call is one fixed lane permutation.
reduceAdd#
pub fn reduceAdd(vector: simd<u8, 32>) -> u8Returns the sum of every lane. Traps when the exact sum does not fit u8.
reduceMinimum#
pub fn reduceMinimum(vector: simd<u8, 32>) -> u8Returns the smallest lane.
reduceMaximum#
pub fn reduceMaximum(vector: simd<u8, 32>) -> u8Returns the largest lane.
wrappingAdd#
pub fn wrappingAdd(left: simd<u8, 32>, right: simd<u8, 32>) -> simd<u8, 32>Returns the sum of each pair of lanes modulo 2^8.
wrappingSubtract#
pub fn wrappingSubtract(left: simd<u8, 32>, right: simd<u8, 32>) -> simd<u8, 32>Returns the difference of each pair of lanes modulo 2^8.
wrappingMultiply#
pub fn wrappingMultiply(left: simd<u8, 32>, right: simd<u8, 32>) -> simd<u8, 32>Returns the product of each pair of lanes modulo 2^8.
saturatingAdd#
pub fn saturatingAdd(left: simd<u8, 32>, right: simd<u8, 32>) -> simd<u8, 32>Returns the sum of each pair of lanes, clamped to the range of u8.
saturatingSubtract#
pub fn saturatingSubtract(left: simd<u8, 32>, right: simd<u8, 32>) -> simd<u8, 32>Returns the difference of each pair of lanes, clamped to the range of u8.
shiftLeft#
pub fn shiftLeft(vector: simd<u8, 32>, counts: simd<u8, 32>) -> simd<u8, 32>Shifts lane i of vector left by lane i of counts.
Gotchas#
Traps when any count is not in the range 0 to 7.
shiftRight#
pub fn shiftRight(vector: simd<u8, 32>, counts: simd<u8, 32>) -> simd<u8, 32>Shifts lane i of vector right by lane i of counts. The shift inserts zero bits.
Gotchas#
Traps when any count is not in the range 0 to 7.
rotateLeft#
pub fn rotateLeft(vector: simd<u8, 32>, counts: simd<u8, 32>) -> simd<u8, 32>Rotates lane i of vector left by lane i of counts modulo 8.
rotateRight#
pub fn rotateRight(vector: simd<u8, 32>, counts: simd<u8, 32>) -> simd<u8, 32>Rotates lane i of vector right by lane i of counts modulo 8.
reduceWrappingAdd#
pub fn reduceWrappingAdd(vector: simd<u8, 32>) -> u8Returns the sum of every lane modulo 2^8.
reduceBitAnd#
pub fn reduceBitAnd(vector: simd<u8, 32>) -> u8Returns the bitwise and of every lane.
reduceBitOr#
pub fn reduceBitOr(vector: simd<u8, 32>) -> u8Returns the bitwise or of every lane.
reduceBitXor#
pub fn reduceBitXor(vector: simd<u8, 32>) -> u8Returns the bitwise exclusive or of every lane.
toI8x32#
pub fn toI8x32(vector: simd<u8, 32>) -> simd<i8, 32>Converts each lane to i8 as the scalar conversion does. Traps when any lane does not
fit i8.
bitcastToI8x32#
pub fn bitcastToI8x32(vector: simd<u8, 32>) -> simd<i8, 32>Returns the bits of vector as a simd<i8, 32>, in memory order.
bitcastToU16x16#
pub fn bitcastToU16x16(vector: simd<u8, 32>) -> simd<u16, 16>Returns the bits of vector as a simd<u16, 16>, in memory order.
bitcastToI16x16#
pub fn bitcastToI16x16(vector: simd<u8, 32>) -> simd<i16, 16>Returns the bits of vector as a simd<i16, 16>, in memory order.
bitcastToU32x8#
pub fn bitcastToU32x8(vector: simd<u8, 32>) -> simd<u32, 8>Returns the bits of vector as a simd<u32, 8>, in memory order.
bitcastToI32x8#
pub fn bitcastToI32x8(vector: simd<u8, 32>) -> simd<i32, 8>Returns the bits of vector as a simd<i32, 8>, in memory order.
bitcastToU64x4#
pub fn bitcastToU64x4(vector: simd<u8, 32>) -> simd<u64, 4>Returns the bits of vector as a simd<u64, 4>, in memory order.
bitcastToI64x4#
pub fn bitcastToI64x4(vector: simd<u8, 32>) -> simd<i64, 4>Returns the bits of vector as a simd<i64, 4>, in memory order.
bitcastToF32x8#
pub fn bitcastToF32x8(vector: simd<u8, 32>) -> simd<f32, 8>Returns the bits of vector as a simd<f32, 8>, in memory order.
bitcastToF64x4#
pub fn bitcastToF64x4(vector: simd<u8, 32>) -> simd<f64, 4>Returns the bits of vector as a simd<f64, 4>, in memory order.
Category: SIMD.
Profiles: aarch64-apple-darwin, aarch64-unknown-linux-gnu, aarch64-unknown-linux-gnu-no-libc, x86_64-unknown-linux-gnu, x86_64-unknown-linux-gnu-no-libc, wasm32-unknown-unknown, wasm32-wasip1, wasm32-wasip2.